The present invention relates to a driver circuit which can be cascade-connected to other driver circuits. More particularly, the present invention relates to a driver circuit used to drive a liquid crystal display (hereinafter abbreviated as "LCD") in particular and which has a circuit for latching therein large quantities of data fed in serial form and outputting the data in parallel therefrom.
As an LCD driver circuit is required to produce a number of outputs, it has a data latch circuit for converting serial data fed from a data generating circuit into parallel data.
The LCD driver circuit having the data latch circuit is normally constructed by a large IC having about 100 terminals. However, such an IC can handle a maximum of 80 outputs. On the other hand, where an IC has about 180 terminals formed by tape automated bonding (hereinafter abbreviated "TAB"), it can handle a maximum of 160 outputs.
Thus, where an electrically processing data system which processes about 640 bits of data is constructed, it is necessary to cascade-connect four to eight driver circuit ICs each of which has 80 to 160 outputs.
In a conventional LCD driver circuit which is cascade-connected to other LCD driver circuits, it is necessary to latch the last serial data based on a latch pulse LP after the last serial data has been transferred. The number of bits (BITS) of data increases in the order of 4, 8 and 12, for example, due to the fact that the screen of an LCD is formed on a large scale. In addition, a clock pulse CP used for the transfer of data also has an increased frequency ranging from 3 MHz through 6 MHz to 8 MHz. Correspondingly, the pulse width of the clock pulse CP becomes narrow. It is therefore necessary to decrease the pulse width of the latch pulse LP corresponding to that of the clock pulse CP. However, when the pulse width of the latch pulse LP is decreased, the present LCD driver circuit is liable to cause malfunctions. When the frequency of the clock pulse CP is 6 MHZ, the pulse width of the corresponding latch pulse LP is about 83 ns. When the frequency of the clock pulse CP is 9 MHZ, the pulse width of the corresponding latch pulse LP is about 62 ns. The pulse width of a latch pulse LP in actual use as an input to the proposed LCD driver circuit is about 50 ns. Thus, the LCD driver circuit is liable to cause malfunctions due to a reduced operating margin. This leads to a bottleneck when a large screen of an LCD is set up.